TAS3001CPWR datasheet(24/56 Pages) TI

tên linh kiện	TAS3001CPWR

Giải thích chi tiết về linh kiện	DIGITAL AUDIO PROCESSOR

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3−4

3.2.5

I2C Serial Port Timing

PARAMETER

MIN

MAX

UNIT

f(scl)

SCL clock frequency

100

kHz

tBUF

Bus free time between start and stop

4.7

µs

tw(low)

Pulse duration, SCL clock low (see Note 1)

4.7

µs

tw(high)

Pulse duration, SCL clock high (see Note 2)

µs

th(STA)

Hold time, repeated start

µs

tsu(STA)

Setup time, repeated start

4.7

µs

th(DAT)

Hold time, data

0†

µs

tsu(DAT)

Setup time, data

250

Rise time for SDA and SCL

1000

Fall time for SDA and SCL

300

tsu(STO)

Setup time for stop condition

µs

† A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.

NOTES:

1. tw(low) is measured from the end of tf to the beginning of tr.

2. tw(high) is measured from the end of tr to the beginning of tf.

Valid

Data Line

Stable

Change of Data

Allowed

SDA

SCL

tBUF

th(STA)

th(DAT)

tsu(DAT)

tsu(STA)

th(STA)

tsu(STO)

Figure 3−4. I2C Serial Port Timing

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