PIC12CE67X datasheet(59/116 Pages) MICROCHIP

59 / 116 page

Preliminary

DS40181B-page 59

PIC12CE67X

FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q3 Q4

Q1 Q2

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q2 Q3

Q1 Q2

OSC1

CLKOUT(4)

GPIO pin

GPIF ﬂag

(INTCON<0>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC+1

PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC+2

Note

XT, HS or LP oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.

GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.

9.9

Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for veriﬁcation purposes.

9.10

ID Locations

Four memory locations (2000h - 2003h) are designated

as ID locations where the user can store checksum or

other code-identiﬁcation numbers. These locations are

not accessible during normal execution but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least signiﬁcant bits of the ID

location are used.

9.11

In-Circuit Serial Programming

PIC12CE67X microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom ﬁrm-

ware to be programmed.

The device is placed into a program/verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

speciﬁcation). GP1 (clock) becomes the programming

clock and GP0 (data) becomes the programming data.

Both GP0 and GP1 are Schmitt Trigger inputs in this

mode.

Note:

Microchip does not recommend code pro-

tecting windowed devices.

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A 6-

bit command is then supplied to the device. Depending

on the command, 14-bits of program data are then sup-

plied to or from the device, depending if the command

was a load or a read. For complete details of serial pro-

gramming, please refer to the PIC12CE67X Program-

ming Speciﬁcations.

FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC12CE67X

VDD

VSS

MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

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