Data Sheet

AD7902

Rev. B | Page 5 of 28

TIMING SPECIFICATIONS

Figure 39, Figure 41, Figure 43, Figure 45, Figure 47, Figure 49, and Figure 51 for timing diagrams.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time (CNVx Rising Edge to Data Available)

t

CONV

500

710

ns

Acquisition Time

t

ACQ

290

ns

Time Between Conversions

t

CYC

VIOx Above 2.3 V

1000

ns

CNVx Pulse Width (CS Mode)

t

CNVH

10

ns

SCKx Period (CS Mode)

t

SCK

VIOx Above 4.5 V

10.5

ns

VIOx Above 3 V

12

ns

VIOx Above 2.7 V

13

ns

VIOx Above 2.3 V

15

ns

SCKx Period (Chain mode)

t

SCK

VIOx Above 4.5 V

11.5

ns

VIOx Above 3 V

13

ns

VIOx Above 2.7 V

14

ns

VIOx Above 2.3 V

16

ns

SCKx Low Time

t

SCKL

4.5

ns

SCKx High Time

t

SCKH

4.5

ns

SCKx Falling Edge to Data Remains Valid

t

HSDO

3

ns

SCKx Falling Edge to Data Valid Delay

t

DSDO

VIOx Above 4.5 V

9.5

ns

VIOx Above 3 V

11

ns

VIOx Above 2.7 V

12

ns

VIOx Above 2.3 V

14

ns

CNVx or SDIx Low to SDOx, D15 (MSB) Valid (CS Mode)

t

EN

VIOx Above 3 V

10

ns

VIOx Above 2.3 V

15

ns

CNVx or SDIx High or Last SCKx Falling Edge to SDOx High Impedance (CS Mode)

t

DIS

20

ns

SDIx Valid Setup Time from CNVx Rising Edge(CS Mode)

t

SSDICNV

5

ns

SDIx Valid Hold Time from CNVx Rising Edge (CS Mode)

t

HSDICNV

2

ns

SCKx Valid Setup Time from CNVx Rising Edge (Chain Mode)

t

SSCKCNV

5

ns

SCKx Valid Hold Time from CNVx Rising Edge (Chain Mode)

t

HSCKCNV

5

ns

SDIx Valid Setup Time from SCKx Falling Edge (Chain Mode)

t

SSDISCK

2

ns

SDIx Valid Hold Time from SCKx Falling Edge (Chain Mode)

t

HSDISCK

3

ns

SDIx High to SDOx High (Chain Mode with Busy Indicator)

t

DSDOSDI

15

ns

Figure 2. Load Circuit for Digital Interface Timing

Figure 3. Voltage Levels for Timing

500µA

500µA

1.4V

TO SDOx

20pF

1

FOR VIOx ≤ 3.0V, X = 90 AND Y = 10; FOR VIOx > 3.0V, X = 70 AND Y = 30.

INPUTS PARAMETER IN TABLE 3.