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AD7761BSTZ bảng dữ liệu(PDF) 65 Page - Analog Devices

tên linh kiện AD7761BSTZ
Giải thích chi tiết về linh kiện  8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW
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AD7761BSTZ bảng dữ liệu(HTML) 65 Page - Analog Devices

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AD7761
Data Sheet
Rev. A | Page 64 of 75
CHANNEL MODE SELECT REGISTER
Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.
Table 37. Bit Descriptions for Channel Mode Select
Bits
Bit Name
Settings
Description
Reset
Access
7
CH_7_MODE
Channel 7
0x0
RW
0
Mode A
1
Mode B
6
CH_6_MODE
Channel 6
0x0
RW
0
Mode A
1
Mode B
5
CH_5_MODE
Channel 5
0x0
RW
0
Mode A
1
Mode B
4
CH_4_MODE
Channel 4
0x0
RW
0
Mode A
1
Mode B
3
CH_3_MODE
Channel 3
0x0
RW
0
Mode A
1
Mode B
2
CH_2_MODE
Channel 2
0x0
RW
0
Mode A
1
Mode B
1
CH_1_MODE
Channel 1
0x0
RW
0
Mode A
1
Mode B
0
CH_0_MODE
Channel 0
0x0
RW
0
Mode A
1
Mode B
POWER MODE SELECT REGISTER
Address: 0x04, Reset: 0x00, Name: POWER_MODE
Table 38. Bit Descriptions for POWER_MODE
Bits
Bit Name
Settings
Description
Reset
Access
7
SLEEP_MODE
In sleep mode, many of the digital clocks are disabled and all of the ADCs are
disabled. The analog LDOs are not disabled.
0x0
RW
The AD7761 SPI is live and is available to the user. Writing to this bit brings
the AD7761 out of sleep mode again.
0
Normal operation.
1
Sleep mode.
[5:4]
POWER_MODE
Power mode. The power mode bits control the power mode setting for the
bias currents used on all ADCs on the AD7761. The user can select the
current consumption target to meet the application. The power modes of
fast, median, and low power give optimum performance when mapped to
the correct MCLK division setting. These power mode bits do not control the
MCLK division of the ADCs. See the MCLK_DIV bits for control of the division
of the MCLK input.
0x0
RW
00
Low power.
10
Median.
11
Fast.
3
LVDS_ENABLE
LVDS clock.
0x0
RW
0
LVDS input clock disabled.
1
LVDS input clock enabled.



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