6

LT3433

3433ia

PI FU CTIO S

SHDN (Pin 11): Shutdown. If the SHDN pin is externally

pulled below 0.5V, low current shutdown mode is initiated.

During shutdown mode, all internal functions are disabled,

a digital input, however, there is a small amount of input

hysteresis built into the SHDN circuit to help assure glitch-

free mode switching. If shutdown is not desired, connect

circuitry is powered from this supply, which is internally

regulated to 2.5V through an on-board linear regulator.

above the regulated voltage allows the use of external power

for much of the LT3433 circuitry. When using external drive,

this pin should be driven above 3V to assure the internal

supply is completely disabled. This pin is typically diode-

connected to the converter output to maximize conversion

efficiency. This pin must be bypassed with at least a 0.1

µF

ceramic capacitor to SGND.

operation in single or 2-switch mode. When the ratios of

the two voltages are such that a >75% duty cycle is required

for regulation, the low side switch is enabled. Drive bias for

the low side switch is also derived directly from this pin.

PWRGND (Pin 14): High Current Ground Reference. This

is the current return for the low side switch and corresponds

to the emitter of the low side switch transistor.

SW_L (Pin 15): Ground Referenced Switch Output. This pin

is the collector of the low side switch transistor. The low

side switch shorts the SW_L pin to PWRGND when enabled.

The series impedance of the ground-referenced switch is

0.6

Ω.