ECT25S40LP1CR datasheet(28/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

Page 28 of 46

4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

this time duration the device will resume normal operation and other instruction will be

accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase,

Program or Write cycle is

process(when WIP equal 1) the instruction is ignored

and

will not have any effects on the current cycle.

Figure 23a. Release Power-Down Sequence Diagram

Figure 23b. Release Power-Down/Read Device ID Sequence Diagram

Read Security Registers (48H)

See Figure 24, the Read Security Registers instruction is similar to Fast Read instruction.

The instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being

latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted

out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of

SCLK.

The first byte addressed can be at any location. The address is automatically incremented

the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches

the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by

driving /CS high.

Address

A23-A16

A15-A8

A7-A0

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

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