ECT25S40 datasheet(3/46 Pages) E-CMOS

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E-CMOS Corp. (www.ecmos.com.tw)

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4L08N-Rev.F001

ECT25S40

4M BIT SPI NOR FLASH

Figure 3. Pin Configuration DIP8L

Signal Description

During all operations, VCC must be held stable and within the specified

valid range: VCC(min) to VCC(max)

All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,VIL or VOL

See

Section “DC Electrical Characteristics”).These signals are described next.

Input / Output Summary

Table 1. Signal Names

Chip Select (/CS)

The chip select signal indicates when a instruction for the device is in process and the other signals are relevant

for the memory device.When the /CS signal is at the logic high state, the device is not selected and all input

signals are ignored and all output signals are high impedance.

Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device will

be in the Standby Power mode. Driving the /CS input to logic low state enables the device, placing it in the

Active Power mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction.

Pin Name

I/O

Description

/CS

Chip Select

SO (IO1)

I/O

Serial Output for single bit data Instructions. IO1 for Dual or Quad

Instructions.

/WP (IO2)

I/O

Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.

The signal has an internal pull-up resistor and may be left unconnected

in the host system if not used for Quad Instructions.

VSS

Ground

SI (IO0)

I/O

Serial Input for single bit data Instructions. IO0 for Dual or Quad

Instructions.

SCLK

Serial Clock

/HOLD (IO3)

I/O

Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in

Quad-I/O mode. The signal has an internal pull-up resistor and may be

left unconnected in the host system if not used for Quad Instructions.

VCC

Core and I/O Power Supply

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