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REF2125 bảng dữ liệu(PDF) 11 Page - Texas Instruments

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tên linh kiện REF2125
Giải thích chi tiết về linh kiện  REF2125 Low-Drift, Low-Power, Small-Footprint, Series Voltage Reference With Clean Start
PDF  24 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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REF2125 bảng dữ liệu(HTML) 11 Page - Texas Instruments

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Solder Heat Shift (%)
0
10%
20%
30%
40%
50%
D017
0
50
100
150
200
250
300
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
11
REF2125
www.ti.com
SBAS798 – SEPTEMBER 2017
Product Folder Links: REF2125
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
7 Parameter Measurement Information
7.1 Solder Heat Shift
The materials used in the manufacture of the REF2125 have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause
the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a
common cause of this error.
In order to illustrate this effect, a total of 32 devices were soldered on four printed circuit boards [16 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in Figure 22. The printed circuit board is comprised of FR4 material. The
board thickness is 1.65 mm and the area is 114 mm × 152 mm.
Figure 22. Reflow Profile
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in Figure 23. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible
depending on the size, thickness, and material of the printed circuit board. An important note is that the
histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is
common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias
voltage. If the PCB is exposed to multiple reflows, solder the device in the second pass to minimize its exposure
to thermal stress.
Figure 23. Solder Heat Shift Distribution, VREF (%)



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