TAS5755MDFD datasheet(5/76 Pages) TI1

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TAS5755M

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SLOS982 – AUGUST 2017

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TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

Pin Functions

TYPE(1)

DESCRIPTION

NAME

NO.

ADR/FAULT

DIO

Dual function terminal which sets the LSB of the 7-bit I2C address to "0" if pulled to GND

and to "1" if pulled to DVDD. If configured to be a fault output by the methods described in

I²C Address Selection and Fault Output, this terminal is pulled low when an internal fault

occurs. A pull-up or pull-down resistor is required, as is shown in the Typical Application

Circuit Diagrams. If pulled high (to DVDD), a 15-kΩ resistor must be used to minimize in-

rush current at power up and to isolate the net if the pin is used as a fault output, as

described above.

AVDD

3.3-V analog power supply

AVSS

13,14

Analog 3.3-V supply ground

BST_A

High-side bootstrap supply for half-bridge A

BST_B

High-side bootstrap supply for half-bridge B

BST_C

High-side bootstrap supply for half-bridge C

BST_D

High-side bootstrap supply for half-bridge D

DVDD

3.3-V digital power supply

DVSS

44,46

Digital ground

DVSS_OSC

Oscillator ground

GVDD

Gate drive internal regulator output

LRCLK

nput serial audio data left/right clock (sample-rate clock)

MCLK

Master clock input

6,7,22,35

,43,45,50

,51

–

No connect

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω, 1% resistor to DVSSO.

OUT_A

20,21

Output, half-bridge A

OUT_B

26,27

Output, half-bridge B

OUT_C

30,31

Output, half-bridge C

OUT_D

36,37

Output, half-bridge D

PBTL

Low means BTL mode; high means PBTL mode. Information goes directly to power stage.

PDNZ

Power down, active-low. PDN prepares the device for loss of power supplies by shutting

down the noise shaper and initiating the PWM stop sequence.

PGND

23,24,25,

32,33,34

Power ground for half-bridges A and B

FLTM

PLL negative loop-filter terminal

FLTP

PLL positive loop-filter terminal

PVDD_AB

18,19

Power-supply input for half-bridge output A and B

PVDD_CD

38,39

Power-supply input for half-bridge output C and D

RESETZ

Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET

is an asynchronous control signal that restores the DAP to its default conditions and

places the PWM in the hard-mute (high-impedance) state.

SCL

I2C serial control clock input

SCLK

Serial audio-data clock (shift clock). SCLK is the serial-audio-port input-data bit clock.

SDA

DIO

I2C serial control data interface input/output

SDIN

Serial audio data input. SDIN supports three discrete (stereo) data formats.

SSTIMER

Controls ramp time of OUT_x to minimize pop. Leave this pin floating for BD mode.

Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp

time.

STEST

Factory test pin. Connect directly to DVSS.

VR_ANA

Internally regulated 1.8-V analog supply voltage. This pin must not be used to power

external devices.

VR_DIG

Internally regulated 1.8-V digital supply voltage. This pin must not be used to power

external devices.

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