IC-MB4 datasheet(32/40 Pages) ICHAUS

32 / 40 page

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iC-MB4

BiSS INTERFACE MASTER

Rev B2, Page 32/40

CONFIGURATION CHANNEL

SLAVELOC5

Addr. 0xEC; bit 4

R/W

Slaves 5-8 are connected to channel 1

Slaves 5-8 are connected to channel 2∗

Table 54: Slave location

CFGIF

Addr. 0xF5; bit 3:2

R/W

0x00

TTL

0x01

CMOS

0x02

RS422∗ † ‡

0x03

LVDS∗ †

Table 55: Configure physical interface

The configuration of both channels control the type of

protocol that is applied by each channel.

CFGCH1

Addr. 0xED; bit 1:0

R/W

CFGCH2∗

Addr. 0xED; bit 3:2

R/W

0x00

BiSS B

0x01

BiSS C

0x02

SSI

0x03

Channel is not used

Table 56: Channel configuration

In previous MB100 or iC-MB3 data sheets this con-

figuration was applied by the former parameter

SELSSI and BISSMOD.

CONFIGURATION SLAVE

ENSCD1

Addr. 0xC0; bit 6

R/W

ENSCD2

Addr. 0xC4; bit 6

R/W

ENSCD3

Addr. 0xC8; bit 6

R/W

ENSCD4

Addr. 0xCC; bit 6

R/W

ENSCD5

Addr. 0xD0; bit 6

R/W

ENSCD6

Addr. 0xD4; bit 6

R/W

ENSCD7

Addr. 0xD8; bit 6

R/W

ENSCD8

Addr. 0xDC; bit 6

R/W

Single cycle data not available

Single cycle data available

Table 57: Enable SCDx

SCDLEN1

Addr. 0xC0; bit 5:0

R/W

SCDLEN2

Addr. 0xC4; bit 5:0

R/W

SCDLEN3

Addr. 0xC8; bit 5:0

R/W

SCDLEN4

Addr. 0xCC; bit 5:0

R/W

SCDLEN5

Addr. 0xD0; bit 5:0

R/W

SCDLEN6

Addr. 0xD4; bit 5:0

R/W

SCDLEN7

Addr. 0xD8; bit 5:0

R/W

SCDLEN8

Addr. 0xDC; bit 5:0

R/W

Single cycle data length = 1

Single cycle data length = 2

Single cycle data length = 3

. . .

Single cycle data length = SCDLENx +1

Single cycle data length = 63

Single cycle data length = 64

Table 58: Length of SCDx (-1)

GRAYS1

Addr. 0xC0; bit 7

R/W

GRAYS2

Addr. 0xC4; bit 7

R/W

GRAYS3

Addr. 0xC8; bit 7

R/W

GRAYS4

Addr. 0xCC; bit 7

R/W

GRAYS5

Addr. 0xD0; bit 7

R/W

GRAYS6

Addr. 0xD4; bit 7

R/W

GRAYS7

Addr. 0xD8; bit 7

R/W

GRAYS8

Addr. 0xDC; bit 7

R/W

SSI single cycle data binary coded

SSI single cycle data gray coded

Table 59: SSI format is Gray code

LSTOP1

Addr. 0xC0; bit 7

R/W

LSTOP2

Addr. 0xC4; bit 7

R/W

LSTOP3

Addr. 0xC8; bit 7

R/W

LSTOP4

Addr. 0xCC; bit 7

R/W

LSTOP5

Addr. 0xD0; bit 7

R/W

LSTOP6

Addr. 0xD4; bit 7

R/W

LSTOP7

Addr. 0xD8; bit 7

R/W

LSTOP8

Addr. 0xDC; bit 7

R/W

No leading STOP bit on single cycle actuator data

Leading STOP bit on single cycle actuator data

Table 60: Actuator stop bit control

∗ The second BiSS interface channel 2 is only available with

iC-MB4 QFN28.

† RS422 and LVDS interfaces are only available with iC-MB4

QFN28.

‡ RS422 interfaces are only operatable with VDD = 4.5 V ... 5.5 V

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