TSC2300 datasheet(21/81 Pages) TI

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TSC2300

SLAS372 — NOVEMBER 2002

In modes where the TSC2300 needs to detect if the screen is still touched (for example, when doing a

PENIRQ-initiated X, Y, and Z conversion), the TSC2300 must reconnect the drivers so that the 50-k

Ω resistor is

connected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs cause a

long delay time, and may prevent the detection from occurring correctly. To prevent this, the TSC2300 has a circuit

which allows any screen capacitance to be precharged through a low-resistance connection to VDD, so that the pullup

resistor doesn’t have to be the only source for the charging current. The time allowed for this precharge, as well as the

time needed to sense if the screen is still touched, can be set in the configuration control register. All other drivers

(X-,Y+, Y-) are off during precharging.

This does point out, however, the need to use the minimum capacitor values possible on the touch screen inputs.

These capacitors may be needed to reduce noise, but too large a value increases the needed precharge and sense

times, as well as panel voltage stabilization time.

In self-controlled modes where the TSC2300 automatically performs conversions when it detects a pen touch, it is

generally not necessary for the host processor to monitor PENIRQ. Instead, the host should monitor DAV, which goes

low when data is available in the appropriate data register, and returns high when all new data has been read back by

the host.

DIGITAL INTERFACE

The TSC2300 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial

communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the

synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize

transmissions.

A transmission begins when initiated by a SPI master. The byte from the SPI master begins shifting in on the slave

MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte shifts out on the

MISO pin to the master shift register.

The idle state of the serial clock for the TSC2300 is LOW, which corresponds to a clock polarity setting of 0 (typical

microprocessor SPI control bit CPOL = 0). The TSC2300 interface is designed so that with a clock phase bit setting of

1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins

driving its MISO pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the

TSC2300 only interprets the first 16 bits transmitted after the falling edge of SS as a command word, and the next 16

bits as a data word only if writing to a register. Reserved register bits should be written to their default values (see

Table 5).

TSC2300 Communication Protocol

The TSC2300 is entirely controlled by registers. Reading and writing these registers is accomplished by the use of a

16-bit command, which is sent prior to the data for that register. The command is constructed as shown in Table 3.

The command word begins with an R/W bit, which specifies the direction of data flow on the serial bus. The following 4

bits specify the page of memory this command is directed to, as shown in Table 2. The next six bits specify the register

address on that page of memory to which the data is directed. The last five bits are reserved for future use.

Table 2. Page Addressing

PG3

PG2

PG1

PG0

PAGE ADDRESSED

reserved

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