RT9107BGPTP datasheet(39/42 Pages) RICHTEK

39 / 42 page

RT9107B

DS9107B-00 November 2016

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 4. Derating Curve of Maximum Power Dissipation

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

where TJ(MAX) is the maximum junction temperature, TAis

the ambient temperature, and

θJA is the junction to ambient

thermal resistance.

For recommended operating condition specifications, the

maximum junction temperature is 125

°C. The junction to

ambient thermal resistance,

θJA, is layout dependent. For

TQFP-48L 7x7 (Exposed Pad) package, the thermal

resistance,

θJA, is 28.9°C/W on a standard JEDEC 51-7

four-layer thermal test board. The maximum power

dissipation at TA = 25

°C can be calculated by the following

formula :

PD(MAX) = (125

°C − 25°C) / (28.9°C/W) = 3.46W for

TQFP-48L 7x7 (Exposed Pad) package

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance,

θJA. The derating curves in Figure 4 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

0.0

0.8

1.6

2.4

3.2

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

Layout Reference

For best performance of the RT9107B, the below PCB

Layout guidelines must be strictly followed.

For higher frequency transients, spikes, or digital hash

on the line, a good low Equivalent-Series-Resistance

(ESR) ceramic capacitor, typically 1

μF, placed as close

as possible to the device PVDD_AB/CD and DVDD pin

lead works best. Placing this decoupling capacitor close

to the RT9107B is very important for the efficiency of the

class-D amplifier, because any resistance or inductance

in the trace between the device and the capacitor can cause

a loss in efficiency. For filtering lower-frequency noise

signals, a 100

μF or greater capacitor placed near the audio

power amplifier would also help. The traces of OUT_A and

OUT_B should be kept equal width and length respectively.

The L+C filter be placed close to chip for better EMI

performance. The power trace of boost inductor is

suggested to be placed on the external layers for higher

current capability. For the case of speaker impedance equal

to 8

Ω, trace width greater than 60mil is recommended.

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