2

PS8103 04/03/97

PI74ALVCH16823

18-BIT BUS-INTERFACE FLIP-FLOP

WITH 3-STATE OUTPUTS

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Inputs

Output

OE

CLR

CLKEN

CLK

D

Q

LL

X

X

X

L

LH

L

↑

HH

LH

L

↑

LL

LH

L

L

X

LH

H

X

X

HX

X

X

X

Z

Product Pin Description

Pin Name

Description

OE

Output Enable Input (Active LOW)

CLR

Clear Input (Active LOW)

CLKEN

Clock Enable Input (Active LOW)

CLK

Clock Input (Active HIGH)

Dx

Data Inputs

Qx

3-State Outputs

GND

Ground

Power

Note:

1. H = High Signal Level

L = Low Signal Level

X = Irrelevant

Z = High Impedance

↑ = LOW-to-HIGH Transition

Product Pin Configuration

1

1CLR

1OE

1Q1

GND

1Q2

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

1Q9

2Q1

2Q2

2Q3

GND

2Q4

2Q5

2Q6

2Q7

2Q8

GND

2Q9

2OE

2CLR

1CLK

1CLKEN

1D1

GND

1D2

1D3

1D4

1D5

1D6

GND

1D7

1D8

1D9

2D1

2D2

2D3

GND

2D4

2D5

2D6

2D7

2D8

GND

2D9

2CLKEN

2CLK

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

25

26

27

28

32

31

30

29

56-Pin

V56

A56