WM8803

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PP Rev 1.1 September 2003

10

The low power modes are listed in Table 1.

MODE

PDB

AMPOPR

PLLOPR

PDOWN1

PDOWN0

FUNCTION

(1)

L

×

×

×

×

Reset (stand-by)

(2)

0

0

0

0

Normal operation

(3)

0

1

0

0

VCO stopped.

(4)

0

×

0

1

All circuits except the oscillator

amplifier stopped.

(5)

0

×

1

0

All circuits except the oscillator

amplifier and divider circuit stopped.

(6)

1

0

0

0

Oscillator amplifier stopped.

(7)

H

1

1

×

×

All circuits stopped.

Table 1 Low Power Modes

The table below lists the output pin states in the above modes.

OUTPUT PIN

MODE (1)

MODE (2)

MODE (3)

MODE (4)

MODE (5)

MODE (6)

MODE (7)

AUDIOB

L

Output

L

L

L

Output

L

UGPIB

H

Output

Output

Output

Output

Output

Output

CLKOUT

L

Output

Output

Output

Output

Output

L

BCLK

L

Output

Output

L

Output

Output

L or H

LRCLK

L

Output

Output

L

Output

Output

L or H

SDATO

L

Output

Output

L

Output

Output

L

XOUT

H

Output

Output

Output

Output

H

H

ERROR

H

Output

H

H

H

Output

H

E/INT

L

Output

L

L

L

Output

L

Table 2 Output Pin States in Modes (1) to (7)

Notes:

1.

In modes (3), (4), and (5), the clock supplied to XIN is used as the source.

2.

Mode (3) applies in the state where an external clock other than CLKOUT is supplied to XIN. If XIN and CLKOUT are

connected, no clock signals are output in this mode.

3.

Mode (6) applies when the PLL circuit is locked. When the PLL circuit is unlocked, all circuits will go to the stopped state

since no clock signal is supplied to XIN.

4.

In mode (7), the states immediately prior to entering mode (7) will be retained.