MPC7457 datasheet(28/68 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Revisions and L3 I/O

Voltage Modes

Unit

Notes

Min

Max

L3_CLK rise and fall time

tL3CR, tL3CF

—

0.75

1, 2

Setup times: Data and parity

tL3DVEH

0.1

—

2, 3

Input hold times: Data and parity

tL3DXEH

—

0.7

2, 3

Valid times: Data and parity

tL3CHDV

—

2.5

2, 4, 5

Valid times: All other outputs

tL3CHOV

—

1.8

Output hold times: Data and parity

tL3CHDX

1.4

—

2, 4, 5

Output hold times: All other outputs

tL3CHOX

1.0

—

2, 5

L3_CLK to high impedance: Data and parity

tL3CHDZ

—

3.0

L3_CLK to high impedance: All other outputs

tL3CHOZ

—

3.0

Notes:

1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.

2. Timing behavior and characterization are currently being evaluated.

3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.

4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load (see

Figure 10).

5. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for

more information.

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