RT5028C datasheet(13/41 Pages) RICHTEK

13 / 41 page

DS5028C-03

September 2016

www.richtek.com

RT5028C

is a registered trademark of Richtek Technology Corporation.

Application Information

The RT5028C is a highly-integrated solution for industrial

system including PMIC and memory system. The

RT5028C application mechanism and I2C compatible

interface are introduced in later sections. The system's

slave address is 0110111 (As SADDR = high) or

0111111(As SADDR = low).

PMIC - Power management system provides 8 low dropout

linear regulator and 4 high efficiency synchronous step-

down DC-DC converters. Power-On and Power-Off

sequences are control by PWRON and RESET input pins.

Detail time sequence control is described in Power ON/

OFF diagram. The I2C interface can program individual

regulator output voltage as well as on/off control and

voltage setting.

I2C Interface Timing Diagram

The RT5028C acts as an I

2C -bus slave. The I2C-bus master

configures the settings for all function blocks by sending

command bytes to the RT5028C via the 2-wire I

2C-bus.

The I

2C timing diagrams are list in the following.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

2C Interface Electrical Characteristics

SDA, SCLK Input High Level

Threshold

0.7 x

VDDA

SDA, SCLK Input Low Level

Threshold

0.3 x

VDDA

SCLK Clock Rate

fSCL

400

kHz

Hold Time (Repeated) START

Condition.

After this period, the first clock

pulse is generated

tHD;STA

0.6

μs

LOW Period of the SCL Clock

tLOW

1.3

μs

HIGH Period of the SCL Clock

tHIGH

0.6

μs

Set-Up Time for a Repeated

START Condition

tSU;STA

0.6

μs

Data Hold Time

tHD;DAT

0.9

μs

Data Set-Up Time

tSU;DAT

100

Set-Up Time for STOP

Condition

tSU;STO

0.6

μs

Bus Free Time Between a

STOP and START Condition

tBUF

1.3

μs

Rise Time of Both SDA and

SCL Signals

300

Fall Time of Both SDA and

SCL Signals

300

SDA and SCL Output Low Sink

Current

IOL

SDA or SCL voltage = 0.4V

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