RT5021 datasheet(54/67 Pages) RICHTEK

54 / 67 page

RT5021

DS5021-01 April 2013

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Address

Name

Bit7

(MSB)

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

(LSB)

Meaning

JEITA

VSETH

VSETC

ISETH

ISETC

CHGSTEN

INT

DPM

Default

0x09

Read/Write

R/W

BAT charge current and regulation voltage control scheme.

JEITA = 0, it means the charger operation is automatic (JEITA rule).

JEITA, VSETH,

VSETC, ISETH, ISETC

JEITA = 1, User can set the VSETH/VSETC to decide the BAT regulate voltage

and set ISETH/ISETC to decide the BAT charge current level. The control

scheme is listed as below.

Used to control CHG pin status.

0 : See FLSH set.

CHGSTEN

1 : Base on charging status.

CHGSTEN = 0 (A9.bit2 = 0)

Charging Status

CHGSTEN = 1

(A9.bit2 = 1)

FLST = 1

(A5.bit7 = 1)

FLST = 0

(A5.bit7 = 0)

No Charging/

Charging Finish

High impedance

(No flashing)

Pre-Charge/

Fast Charge

0.5Hz (2s)

Abnormal (Fault timer

timeout, in thermal

regulation, battery too

cold or too hot

4Hz (0.25s)

High

Impedance

Low

Control the output of INT open drain port. The bit value is inverted of INT output.

When interrupt events happen, INT port goes low and this bit A9. INT would be

triggered to 1. Micro-processor must write this bit to be 0 for making INT go high.

0 : INT = High

INT

1 : INT = Low

The DPM bit is the charger VIN DPM status bit. It means the charger DPM (VIN

falls and regulates at 4.35V) is activated or not.

0 : VIN DPM not activated.

1 : VIN DPM activated (working).

DPM

Note : when PMU turns on, it would check the bit DPM and compare to the value

0. If it is different, INT would be asserted. After PMU is on, once DPM bit toggles,

INT also asserts again.

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