DAC38RF80 datasheet(9/155 Pages) TI1

9 / 155 page

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

www.ti.com

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

DAC38RF83 DAC38RF93

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Pin Functions - DAC38RF83, DAC38RF93, DAC38RF85 (continued)

I/O

DESCRIPTION

NAME

NO.

SYSREF+

LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This

positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC

synchronization.

SYSREF-

LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+

description)

TCLK

JTAG test clock. Internal pull-down

TDI

JTAG test data in. Internal pull-up

TDO

JTAG test data out. Internal pull-up

TESTMODE

This pin is used for factory testing.

Recommended to connect to ground for normal operation.

TMS

JTAG test mode select. Internal pull-up

TRST

JTAG test reset. Internal pull-up. Must be connected to ground if not used

TXENABLE

Transmit enable active high input. Internal pull-down.

This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission.

To enable analog output data transmission, pull the CMOS TXENABLE pin to high.

To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.

VDDA1

F11, J11

Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance.

VDDA18

G11, H11

Analog 1.8 V supply voltage. (1.8 V)

VDDPLL1

D8, E8

Analog 1 V supply for PLL.

VDDAPLL18

B9, B10

PLL analog supply voltage. (1.8 V)

VDDAVCO18

D9, E9

Analog supply voltage for VCO (1.8 V)

VDDCLK1

G9, H9

Internal clock buffer supply voltage (1 V).

It is recommended to isolate this supply from VDDDIG1 and VDDA1.

VDDL1_1

G8, H8

DAC core supply voltage. (1 V)

VDDL2_1

G10, H10

DAC core supply voltage. (1 V)

VDDDIG1

A5, B5, C5, D5, D7, E3,

E4, E5, E6, F4, F5, G4,

Digital supply voltage. (1 V).

It is recommended to isolate this supply from VDDCLK1 and VDDA1.

VDDE1

F7, H7, G6, J6

Digital Encoder supply voltage (1 V).

Must be separated from VDDDIG1 supply for best performance.

VDDIO18

Supply voltage for all digital I/O and CMOS I/O (1.8 V).

VDDOUT18

G12, H12

DAC output supply. (1.8 V)

VDDR18

H2, J2

Supply voltage for SerDes. (1.8 V)

VDDS18

B3, B4

Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V)

VDDT1

H3, J3

Supply voltage for SerDes termination. (1 V)

VDDTX1

Supply voltage for divided clock output. (1 V)

VDDTX18

Supply voltage for divided clock output . (1.8 V)

VEE18N

D10, E10, K10, L10

Analog supply voltage. (-1.8 V)

VOUT1+

L12

DAC channel 1 output.

VOUT1-

K12

DAC channel 1 complementary output.

VOUT2+

D12

DAC channel 2 output. Leave pin floating in DAC38RF85

VOUT2-

E12

DAC channel 2 complementary output. Leave pin floating in DAC38RF85

VSENSE

Test pin for on chip parametrics. Can be left floating.

VSSCLK

A8, A11, B8, B11, B12,

F8, F9, F10, J8, J9, J10

Clock ground.

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