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RT4531WSC bảng dữ liệu(PDF) 5 Page - Richtek Technology Corporation |
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RT4531WSC bảng dữ liệu(HTML) 5 Page - Richtek Technology Corporation |
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5 / 14 page ![]() 5 RT4531 DS4531-01 July 2016 www.richtek.com © Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Maximum Duty Cycle DMAX 90 95 -- % Back Light N-MOSFET Ron RDS(ON)_BLN 100 270 400 m Back Light Current Limit ILIM_BL After 5ms in soft-start 1.15 1.5 1.85 A Back Light Over Voltage Protection VBLOVP Close loop, VIN = 3.6V 35.5 36.5 37.5 V IFBx Pin Over Voltage Threshold VIFBXOVP Measure on IFBx pin -- 5 -- V Logic Control One Wire Detection Delay tes_delay Measure from En low to high 300 -- -- s One Wire Detection Time tes_det En pin low time in detection window 400 -- -- s One Wire Detection Window tes_win Measure from En low to high, Fblosc = 1MHz -- 1 -- ms Start Time of Program Stream tstart 3 -- -- s End Time of Program Stream tEOS 3 -- -- s High Time Low Bit tH_LB Logic 0 2 -- 180 s Low Time Low Bit tL_LB Logic 0 2 x tH_LB -- 360 s High Time High Bit tH_HB Logic 1 2 x tL_HB -- 360 s Low Time High Bit tL_HB Logic 1 2 -- 180 s EN Input Voltage Logic-Low VEN_L -- -- 0.4 V Logic-High VEN_H 1.4 -- -- PWM Input Voltage Logic-Low VPWM_L -- -- 0.4 V Logic-High VPWM_H 1.4 -- -- EN Pull Low Resistor REN 280 400 520 k PWM Pull Low Resistor RPWM 280 400 520 k PWM Logic Low Width to Shutdown TSD_PWM PWM pin high to low, then shutdown 20 -- -- ms EN Logic Low Width to Shutdown TDS_EN EN pin high to low, then shutdown 2.5 -- -- ms Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. |
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