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RT9750WSC bảng dữ liệu(PDF) 7 Page - Richtek Technology Corporation

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RT9750
7
DS9750-01 June 2017
www.richtek.com
©
Copyright 2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VBUS ADC Range
VBUS_ADC_RAN
VDDA > 3V, 16 averages
1.5
--
6.5
V
VBUS ADC Accuracy
VBUS_ADC_ACC
15
--
15
mV
IBUS ADC Range
IBUS_ADC_RAN
VDDA > 3V, 16 averages
0
--
7
A
IBUS ADC Accuracy
IBUS_ADC_ACC
200
--
200
mA
VOUT ADC Range
VOUT_ADC_RAN
VDDA > 3V, 16 averages
1.5
--
6.5
V
VOUT ADC Accuracy
VOUT_ADC_ACC
15
--
15
mV
VDROP ADC Range
VDROP_ADC_RAN
VDDA > 3V, 16 averages
0
--
1000
mV
VDROP ADC Accuracy
VDROP_ADC_ACC
15
--
15
mV
VBAT ADC Range
VBAT_ADC_RAN
VDDA > 3V, 16 averages
2.5
--
5
V
VBAT ADC Accuracy
VBAT_ADC_ACC
15
--
15
mV
TSVBUS ADC Range
VTSVBUS_ADC_RAN
VDDA > 3V, 16 averages
0
--
2.4
V
TSVBUS ADC Accuracy VTSVBUS_ADC_ACC
15
--
15
mV
TSBAT ADC Range
VTSBAT_ADC_RAN
VDDA > 3V, 16 averages
0
--
2.4
V
TSBAT ADC Accuracy
VTSBAT_ADC_ACC
15
--
15
mV
Junction Thermal ADC
Range
TJC_ADC_RAN
VDDA > 3V, 16 averages
0
--
125
°C
Junction Thermal ADC
Accuracy
TJC_ADC_ACC
3
--
3
°C
I
2C Interface
Serial-Clock Frequency
fSCL_I2C
(Note 5)
10
--
1000
kHz
I2C Input Logic
Threshold
VIH_I2C
Logic high
1.5
--
--
V
VIL_I2C
Logic low
--
--
0.4
V
EN Input
EN Input Logic
Threshold
VIH_EN
Logic high
1
--
--
V
VIL_EN
Logic low
--
--
0.4
V
EN Pull Down Resistor
RPD_EN
On chip
--
500
--
k
Device turn-on delay
time after EN pull-high
--
--
500
s
Note 1.
Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2.
θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 3.
Devices are ESD sensitive. Handling precaution is recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Note 5.
Specification is guaranteed by design and/or correlation with statistical process control.



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