RT9428WSC datasheet(5/14 Pages) RICHTEK

5 / 14 page

RT9428

DS9428-01

October 2014

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

2C Interface

Clock Operating Frequency

fSCL

(Note 7)

250

kHz

Bus Free Time Between a

STOP and START Condition

tBUF

1.3

s

Hold Time After START

Condition

tHD_STA

(Note 7)

0.6

s

Low Period of the SCL Clock

tLOW

1.3

s

High Period of the SCL Clock tHIGH

0.6

s

Setup Time for a Repeated

START Condition

tSU_STA

0.6

s

Data Hold Time

tHD_DAT

(Note 8, Note 9)

0.2

0.9

Data Setup Time

tSU_DAT

(Note 8)

100

Clock Data Rising Time

300

Clock Data Falling Time

300

Set-Up Time for STOP

Condition

tSU_STO

0.6

s

Spike Pulse Widths

Suppressed by Input Filter

tSP

(Note 10)

Capacitive Load for Each Bus

Line

(Note 11)

400

SCL, SDA Input Capacitance

CBIN

Note 1. Stresses beyond those listed

“Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2.

θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. The device is not guaranteed to function outside its operating conditions.

Note 4. Specifications are 100% tested at TA = 25

°C. Limits over the operating range are guaranteed by design and

characterization.

Note 5. SDA, SCL = GND; QS, ALERT idle.

Note 6. The RT9428 enter sleep mode after SCL and SDA low for longer than 3s.

Note 7. fSCL must meet the minimum clock low time plus the rise/fall time.

Note 8. The maximum tHD_DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 9. This device internally provides a hold time of at least 75ns for the SDA signal to bridge the undefined region of the

falling edge of SCL.

Note 10. Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

Note 11. CB total capacitance of one bus line in pF.

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