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ICS951412 bảng dữ liệu(PDF) 10 Page - Integrated Circuit Systems |
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ICS951412 bảng dữ liệu(HTML) 10 Page - Integrated Circuit Systems |
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10 / 10 page ![]() 10 ICS951412 0883G—12/08/04 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1 Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1 Input High Current IIH VIN = VDD -5 5 uA 1 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Operating Current IDD3.3OP all outputs driven 300 mA Input Frequency 3 Fi VDD = 3.3 V 14.31818 MHz 3 Pin Inductance 1 Lpin 7nH 1 CIN Logic Inputs 5 pF 1 COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins 5 pF 1 Clk Stabilization 1,2 TSTAB From VDD Power-Up or de-assertion of PD# to 1st clock 3ms 1,2 Modulation Frequency Triangular Modulation 30 33 kHz 1 SMBus Voltage VDD 2.7 5.5 V 1 Low-level Output Voltage VOL @ IPULLUP 0.4 V 1 Current sinking at VOL = 0.4 V IPULLUP 4mA 1 SCLK/SDATA Clock/Data Rise Time 3 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 SCLK/SDATA Clock/Data Fall Time 3 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1Guaranteed by design and characterization, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. Input Low Current Input Capacitance 1 |
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