ICS854058 datasheet(9/12 Pages) ICST

9 / 12 page

854058AG

www.icst.com/products/hiperclocks.html

REV. A APRIL 8, 2004

Integrated

Circuit

Systems, Inc.

ICS854058

8:1

DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER

PRELIMINARY

SCHEMATIC EXAMPLE

An application schematic example of ICS854058 is shown

Figure 4. The inputs can accept various types of differential

signals. In this example, the inputs are driven by LVDS drivers.

The transmission lines are assumed to be 100

Ω differential.

The 100

Ω matched loads termination should be located

near the receivers. It is recommended at least one

decoupling capacitor per power pin. The decoupling ca-

pacitor should be low ESR and located as close as pos-

sible to the power pin.

FIGURE 4. ICS854058 SCHEMATIC EXAMPLE

100

100 Ohm Differential

Zo = 50

3.3V

VDD

ICS854058

PCLK0

nPCLK0

PCLK1

nPCLK1

VDD

SEL0

SEL1

SEL2

PCLK2

nPCLK2

PCLK3

nPCLK3

nPCLK4

PCLK4

nPCLK5

PCLK5

GND

nQ0

VDD

PCLK7

nPCLK7

PCLK6

nPCLK6

0.1u

Zo = 50

3.3V

RU1

Set Logic

Input to

'0'

0.1u

LVDS

To Logic

Input

pins

100 Ohm Dif ferential

RD1

Not Install

To Logic

Input

pins

100

LVDS

Logic Control Input Examples

LVDS

Set Logic

Input to

'1'

Zo = 50

100

RD2

Zo = 50

VDD

Zo = 50

100 Ohm Differential

RU2

Not Install

Zo = 50

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