ICS843031 datasheet(6/11 Pages) ICST

6 / 11 page

843031AG

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 29, 2004

Integrated

Circuit

Systems, Inc.

ICS843031

FEMTOCLOCKS™CRYSTAL-TO-

3.3V LVPECL CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 1. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS843031 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 1 below were determined using a 26.04167MHz, 18pF

parallel resonant crystal and were chosen to minimize the ppm

error. The optimum C1 and C2 values can be slightly adjusted

for different board layouts.

18pF Parallel Cry stal

12p

XTAL_OUT

XTAL_IN

12p

TERMINATION FOR 3.3V LVPECL OUTPUT

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

FIGURE 2B. LVPECL OUTPUT TERMINATION

FIGURE 2A. LVPECL OUTPUT TERMINATION

drive 50

Ω transmission lines.Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 2A and 2B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

CC - 2V

Ω

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

Ω

125

Ω

o = 50Ω

FOUT

FIN

ICS843031 bảng dữ liệu(PDF) 6 Page - Integrated Circuit Systems

ICS843031 bảng dữ liệu(HTML) 6 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11

bảng dữ liệu tải về

Link URL