5

ICS93V857-XXX

0693K—03/13/03

Notes:

1.

Refers to transition on noninverting output in PLL bypass mode.

2.

While the pulse skew is almost constant over frequency, the duty cycle error

3.

Switching characteristics guaranteed for application frequency range.

4.

Static phase offset shifted by design.

Timing Requirements

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Max clock frequency

3

2.5V+0.2V

33

233

MHz

Application Frequency

Range

3

2.5V+0.2V

60

170

MHz

Input clock duty cycle

40

60

%

CLK stabilization

100

µs

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Low-to high level

propagation delay time

1

CLK_IN to any output

5.5

ns

High-to low level propagation

delay time

1

CLK_IN to any output

5.5

ns

Output enable time

PD# to any output

5

ns

Output disable time

PD# to any output

5

ns

Period jitter

66/100/125/133/167MHz

-40

40

ps

100 to <170MHz

-100

100

ps

≥170MHz to 233MHz

-120

50

ps

Input clock slew rate

14

v/ns

Output clock slew rate

66/100/133/167MHz

1

2

v/ns

Cycle to Cycle Jitter

1

66/100/125/133/167MHz

60

ps

Phase error

4

-50

0

50

ps

Output to Output Skew

40

60

ps

Rise Time, Fall Time

Load = 120

Ω/16pF

650

800

950

ps

Half-period jitter