HT49C30L datasheet(12/43 Pages) HOLTEK

12 / 43 page

HT49R30A-1/HT49C30-1/HT49C30L

Rev. 1.10

September 25, 2002

not full, and the TF bit is set, a subroutine call to location

0CH occurs. The related interrupt request flag (TF) is re-

set, and the EMI bit is cleared to disable further inter-

rupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF; bit 4 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 10H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 5 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

14H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the

²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine,

²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

No.

Interrupt Source

Priority Vector

External interrupt 0

04H

External interrupt 1

08H

Timer/event counter overflow

0CH

Time base interrupt

10H

Real time clock interrupt

14H

The timer/event counter interrupt request flag (TF), ex-

ternal interrupt 1 request flag (EIF1), external interrupt 0

request flag (EIF0), enable timer/event counter interrupt

bit (ETI), enable external interrupt 1 bit (EEI1), enable

external interrupt 0 bit (EEI0), and enable master inter-

rupt bit (EMI) make up of the Interrupt Control register 0

(INTC0) which is located at 0BH in the RAM. The real

time clock interrupt request flag (RTF), time base inter-

rupt request flag (TBF), enable real time clock interrupt

bit (ERTI), and enable time base interrupt bit (ETBI),

constitute the Interrupt Control register 1 (INTC1) which

is located at 1EH in the RAM. EMI, EEI0, EEI1, ETI,

ETBI, and ERTI are all used to control the enable/dis-

able status of interrupts. These bits prevent the re-

quested interrupt from being serviced. Once the

interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all

set, they remain in the INTC1 or INTC0 respectively until

the interrupts are serviced or cleared by a software in-

struction.

Bit No.

Label

Function

INTC0

(0BH)

EMI

Control the master (global) interrupt (1=enabled; 0=disabled)

EEI0

Control the external interrupt 0 (1=enabled; 0=disabled)

EEI1

Control the external interrupt 1 (1=enabled; 0=disabled)

ETI

Control the timer/event counter interrupt (1=enabled; 0=disabled)

EIF0

External interrupt 0 request flag (1=active; 0=inactive)

EIF1

External interrupt 1 request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC1

(1EH)

ETBI

Control the time base interrupt (1=enabled; 0:disabled)

ERTI

Control the real time clock interrupt (1=enabled; 0:disabled)

2, 3

Unused bit, read as

²0²

TBF

Time base request flag (1=active; 0=inactive)

RTF

Real time clock request flag (1=active; 0=inactive)

6, 7

Unused bit, read as

²0²

INTC register

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