EM6517 datasheet(8/64 Pages) EMMICRO

8 / 64 page

EM6517

03/02 REV. C/448

 2002, EM Microelectronic-Marin SA

www.emmicroelectronic.com

Reset

Figure 8. illustrates the reset structure of the EM6517-1. There are six possible reset sources :

(1) Internal initial reset from the Power On Reset (POR) circuitry.

--> POR

(2) External reset from the Reset terminal.

--> System Reset, Reset CPU

(3) External reset by simultaneous high/low inputs to port A.

--> System Reset, Reset CPU

(Combinations are defined in the registers OptInpRSel1 and OptInpRSel2)

(4) Internal reset from the Digital Watchdog.

--> System Reset, Reset CPU

(5) Internal reset from the Oscillation Detection Circuit.

--> System Reset, Reset CPU

(6) Internal reset when sleep mode is activated.

--> System Reset, Reset CPU

All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the

system reset remains active long enough for all system functions to be reset (active for n system clock cycles).

The ‘CPU Reset Delay’ ensures that the reset CPU remains active until the oscillator is in stable oscillation.

As well as activating the system reset and the reset CPU, the POR also resets all option registers and the sleep

enable (SleepEn) latch. System reset and reset CPU do not reset the option registers nor the SleepEn latch.

Reset state can be shown on Strobe terminal by selecting StrobeOutSel1,0 = 0 in OPTCandStr register.

5.1 Oscillation Detection Circuit

At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry,

and thus the system reset. The CPU of the EM6517 remains in the reset state for the ‘CPU Reset Delay’, to

allow the oscillator to stabilize after power up.

Figure 8. Reset Structure

S y ste m R e se t

De la y

CP U Re s e t

De la y

E nab le

A c tiv a te

Dig ita l

W a tc hdog

O s c illa tio n

De te c tio n

R e s e t f ro m P o r t A

Input C o m b in a tio n

Re s e t P A D

S leep

O p tIn p R S leep

Re s e t

CPU

Inhibit

Os c illa tio n

De te c tio n

Inhibit

Dig ita l

W a tc hd og

PO R

P O R to O p tio n

R egis te r s & S leepE n

La tc h

DE B O UN CE

S leep

Latc h

Sle e p En

La tc h

PO R

In te r n a l D a ta B u s

Write R e s e t

R ead S tatus

Write A c tiv e

R ead S ta tus

Ck [1 0 ]

Ck [1 ]

Ck [8 ]

Ck [1 ]

C k [15]

PO R

A nalo gue

F ilte r

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