WM8805 datasheet(13/66 Pages) CIRRUS

13 / 66 page

Production Data

WM8805

PD, Rev 4.5, March 2009

When the device powers up, all power up configuration pins are configured as inputs for a minimum

of 9.4us and a maximum of 25.6us following the release of the external reset. The times are based

on 27MHz and 10MHz crystal clock frequencies respectively. This enables the pins to be sampled

and the device to be configured before the pins are released to their selected operating conditions.

Figure 7 illustrates how SDIN is sampled.

Figure 7 Pin Sampling On Power Up or Hardware Reset

If the device is powered up in Software control mode, all functions of the device are powered down by

default and must be powered up individually by writing to the relevant bits of the PWRDN register

(Table 7). In Hardware Control Mode, all functions of the device are powered up by default.

BIT

LABEL

DEFAULT

DESCRIPTION

R30

PWRDN

1Eh

PLLPD

PLL Powerdown

0 = PLL enabled

1 = PLL disabled

SPDIFRXP

S/PDIF Receiver Powerdown

0 = S/PDIF receiver enabled

1 = S/PDIF receiver disabled

SPDIFTXPD

S/PDIF Transmitter

Powerdown

0 = S/PDIF transmitter enabled

1 = S/PDIF transmitter disabled

OSCPD

Oscillator Power Down

0 = Power Up

1 = Power Down

AIFPD

Digital Audio Interface Power

Down

0 = Power Up

1= Power Down

TRIOP

Tri-state all Outputs

0 = Outputs not tri-stated

1 = Outputs tri-stated

Table 7 Power Down Register

ENB

SDIN

RSTB

Power-

On Reset

POR_B

HWMODE

SWMODE

Sampling of pin value at reset to

generate internal signals.

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