WM0011 datasheet(21/233 Pages) CIRRUS

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WM0011

Production Data

PD, Rev 4.1, August 2013

SPI INTERFACE – SLAVE MODE

SPISS

(input)

SPISCLK

(input)

SPIMOSI

(input)

tSSU

tSCY

tDHO

tDSU

tSHO

SPIMISO

(output)

TX_PHASE=0

tDL

tEDL

SPIMISO

(output)

TX_PHASE=1

tDZ

tZD

Figure 5 SPI Slave Mode Timing

Note this diagram shows the mode where incoming data (SPIMOSI) is sampled on the rising edge of

SPISCLK. By default, the outgoing data (SPIMISO) transitions on the falling edge of SPISCLK. When

‘Early Transmit Data Phase’ mode is selected (TX_PHASE=1), the outgoing data (SPIMISO)

transitions on the rising edge of SPISCLK.

Test Conditions

AVDD=DCVDD=1.2V, DBVDD1=DBVDD2=DBVDD3=1.8V, TA = +25°C, CLOAD=5pF (output pins), unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

SPI Interface Timing - Slave Mode

SPISS

¯¯¯¯¯ set-up time to SPISCLK rising edge

tSSU

tAHBCLK +

1.0

SPISS

¯¯¯¯¯ hold time from SPISCLK falling edge

tSHO

2.0

SPISCLK pulse cycle time

tSCY

38.5

In SPI Slave mode, the maximum SPISCLK frequency is 26MHz. It is also required that FSPISCLK < FAHBCLK.

SPISCLK duty cycle

SPIMOSI set-up time to SPISCLK rising edge

tDSU

2.0

SPIMOSI hold time from SPISCLK rising edge

tDHO

2.0

SPIMISO propagation delay from

SPISCLK falling edge

CLOAD=25pF

tDL

12.1

CLOAD=5pF

9.3

SPIMISO propagation delay from

SPISCLK rising edge (early TX data mode)

CLOAD=25pF

tEDL

14.1

CLOAD=5pF

11.3

SPIMISO enable from SPISS

¯¯¯¯¯ falling edge

tZD

13.6

SPIMISO disable from SPISS

¯¯¯¯¯ rising edge

tDZ

7.8

Table 6 SPI Slave Mode Timing Values

Note the timing figures quoted in the table above are for full drive strength outputs; these timings are

not guaranteed for reduced drive strength.

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