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WM8912 bảng dữ liệu(PDF) 81 Page - Cirrus Logic

tên linh kiện WM8912
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WM8912 bảng dữ liệu(HTML) 81 Page - Cirrus Logic

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Production Data
WM8912
w
PD, Rev 4.1, February 2013
81
The sequence of signals associated with a single register write operation is illustrated in Figure 46.
Figure 46 Control Interface Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 47.
Figure 47 Control Interface Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 55.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM8912
register map faster than is possible with single register operations.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
A
¯¯
Not Acknowledge (SDA High)
P
Stop Condition
R/W
¯¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM8912
[Grey field]
Data flow from WM8912 to bus master
Table 55 Control Interface Terminology
Figure 48 Single Register Write to Specified Address



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