WM8523 datasheet(21/46 Pages) CIRRUS

tên linh kiện	WM8523

Giải thích chi tiết về linh kiện	24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

PDF	46 Pages

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Production Data

WM8523

PD, Rev 4.2, August 2013

In DSP mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A) rising edge of

BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately

follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be

unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 19 and Figure

20. In device slave mode, Figure 21 and Figure 22, it is possible to use any length of frame pulse less

than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the

rising edge of the next frame pulse.

Figure 19 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)

Figure 20 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)

Figure 21 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)

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