W78C32C/W78C032C

Publication Release Date: December 4, 2006

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Revision A6

5.3.2

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode

all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a

reset.

5.3.3

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two

machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C032C is used

with an external RC network. The reset logic also has a special glitch removal circuit that ignores

glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit

4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.