HT46R003B datasheet(39/76 Pages) HOLTEK

39 / 76 page

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HT46R003B

Cost-Effective A/D 8-bit OTP MCU

HT46R003B

Cost-Effective A/D 8-bit OTP MCU

IftheActiveEdgeSelectbitTEGwhichisbit3oftheTimerControlRegisterislow,onceahigh

tolowtransitionhasbeenreceivedontheexternaltimerpin,theTimer/EventCounterwillstart

countinguntiltheexternaltimerpinreturnstoitsoriginalhighlevel.Atthispointtheenablebitwill

beautomaticallyresettozeroandtheTimer/EventCounterwillstopcounting.IftheActiveEdge

Selectbitishigh,theTimer/EventCounterwillbegincountingoncealowtohightransitionhas

beenreceivedontheexternaltimerpinandstopcountingwhentheexternaltimerpinreturnstoits

originallowlevel.Asbefore,theenablebitwillbeautomaticallyresettozeroandtheTimer/Event

Counterwillstopcounting.Itisimportanttonotethatinthepulsewidthcapturemode,theenable

bitisautomaticallyresettozerowhentheexternalcontrolsignalontheexternaltimerpinreturns

toitsoriginallevel,whereasintheothertwomodestheenablebitcanonlyberesettozerounder

programcontrol.

TheresidualvalueintheTimer/EventCounter,whichcannowbereadbytheprogram,therefore

representsthelengthofthepulsereceivedontheTMRpin.Astheenablebithasnowbeenreset,

anyfurthertransitionsontheexternaltimerpinwillbeignored.Thetimercannotbeginfurtherpulse

widthcaptureuntiltheenablebitissethighagainbytheprogram.Inthisway,singleshotpulse

measurementscanbeeasilymade.ItshouldbenotedthatinthismodetheTimer/EventCounteris

controlledbylogicaltransitionsontheexternaltimerpinandnotbythelogiclevel.WhentheTimer/

EventCounterisfullandoverflows,aninterruptsignalisgeneratedandtheTimer/EventCounter

willreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.Theinterrupt

canbedisabledbyensuringthattheTimer/EventCounterInterruptEnablebitinthecorresponding

InterruptControlRegister,itisresettozero.AstheTMRpinissharedwithanI/Opin,toensure

thatthepinisconfiguredtooperateasapulsewidthcapturepin,twothingshavetobeimplemented.

ThefirstistoensurethattheOperatingModeSelectbitsintheTimerControlRegisterplacethe

Timer/EventCounterinthepulsewidthcapturemode,thesecondistoensurethattheportcontrol

registerconfigurethepinasaninput.

Ti me r

Ex te rn al T MR

Pi n I npu t

TO N - wi th T EG =0

In te r nal C lo ck o r

Pr e sca le r Ou t put

In cr em en t

Ti me r C oun te r

Pr e sca le r Ou t p ut i s sa m p le d at e ve r y fa lli n g e d g e of T 1.

Pulse Width Capture Mode Timing Chart (TEG=0)

Prescaler

BitsTPSC2~TPSC0oftheTMRCregistercanbeusedtodefineadivisionratiofortheinternal

clocksourceoftheTimer/EventCounterenablinglongertimeoutperiodstobeset.

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