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R5F56519FDFP bảng dữ liệu(PDF) 149 Page - Renesas Technology Corp

tên linh kiện R5F56519FDFP
Giải thích chi tiết về linh kiện  120-MHz, 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 1-MB flash memory,
PDF  190 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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R5F56519FDFP bảng dữ liệu(HTML) 149 Page - Renesas Technology Corp

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R01DS0276EJ0100 Rev.1.00
Page 149 of 190
Aug 24, 2016
RX65N Group, RX651 Group
5. Electrical Characteristics
Note 1. tPBcyc: PCLKB cycle
Figure 5.41
A/D Converter Trigger Input Timing
Note 1. tPBcyc: PCLKB cycle
Note 2. tcac: CAC count clock source cycle
Table 5.30
A/D Converter Trigger Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF,
High-drive output is selected by the driving ability control register.
Item
Symbol
Min.
Max.
Unit*1
Test
Conditions
A/D
converter
A/D converter trigger input pulse width
tTRGW
1.5
—
tPBcyc
Figure 5.41
Table 5.31
CAC Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF,
High-drive output is selected by the driving ability control register.
Item*1, *2
Symbol
Min.*1
Max.
Unit*1
Test
Conditions
CAC
CACREF input pulse width
tPBcyc ≤ tcac
tCACREF
4.5 tcac +
3 tPBcyc
—ns
tPBcyc > tcac
5 tcac +
6.5 tPBcyc
—
ADTRG0#,
ADTRG1#
PCLKB
tTRGW



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