R5F104LEG datasheet(85/213 Pages) RENESAS

85 / 213 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

°C)

R01DS0053EJ0330 Rev. 3.30

Page 85 of 208

Aug 12, 2016

Note 1.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 2.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 3.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from

SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 4.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

Remark 1.

This value is valid only when CSI00’s peripheral I/O redirect function is not used.

Remark 2.

p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),

g: PIM and POM numbers (g = 1)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00))

(2)

During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corre-

sponding CSI00 only)

(TA = -40 to +85°C, 2.7 V

≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) mode

LS (low-speed

main) mode

LV (low-voltage

main) mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

SCKp cycle time

tKCY1

≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V

62.5

250

500

2.7 V

≤ EVDD0 ≤ 5.5 V

83.3

250

500

SCKp high-/low-level

width

tKH1,

tKL1

4.0 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 - 7

tKCY1/2 - 50

2.7 V

≤ EVDD0 ≤ 5.5 V

tKCY1/2 - 10

tKCY1/2 - 50

SIp setup time (to SCKp↑)

Note 1

tSIK1

4.0 V

≤ EVDD0 ≤ 5.5 V

110

2.7 V

≤ EVDD0 ≤ 5.5 V

110

SIp hold time (from

SCKp↑) Note 2

tKSI1

2.7 V

≤ EVDD0 ≤ 5.5 V

Delay time from SCKp↓ to

SOp output Note 3

tKSO1

C = 20 pF Note 4

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