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R5F104LED bảng dữ liệu(PDF) 89 Page - Renesas Technology Corp

tên linh kiện R5F104LED
Giải thích chi tiết về linh kiện  True Low Power Platform
PDF  213 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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R5F104LED bảng dữ liệu(HTML) 89 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85
°C)
R01DS0053EJ0330 Rev. 3.30
Page 89 of 208
Aug 12, 2016
Caution
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark
p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2.
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
(4)
During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +85°C, 1.6 V
≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(2/2)
Parameter
Symbol
Conditions
HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SSI00 setup time
tSSIK
DAPmn = 0 2.7 V
≤ EVDD0 ≤ 5.5 V
120
120
120
ns
1.8 V
≤ EVDD0 ≤ 5.5 V
200
200
200
ns
1.7 V
≤ EVDD0 ≤ 5.5 V
400
400
400
ns
1.6 V
≤ EVDD0 ≤ 5.5 V
—
400
400
ns
DAPmn = 1 2.7 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 120
1/fMCK + 120
1/fMCK + 120
ns
1.8 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 200
1/fMCK + 200
1/fMCK + 200
ns
1.7 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 400
1/fMCK + 400
1/fMCK + 400
ns
1.6 V
≤ EVDD0 ≤ 5.5 V
—1/fMCK + 400
1/fMCK + 400
ns
SSI00 hold time
tKSSI
DAPmn = 0 2.7 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 120
1/fMCK + 120
1/fMCK + 120
ns
1.8 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 200
1/fMCK + 200
1/fMCK + 200
ns
1.7 V
≤ EVDD0 ≤ 5.5 V 1/fMCK + 400
1/fMCK + 400
1/fMCK + 400
ns
1.6 V
≤ EVDD0 ≤ 5.5 V
—1/fMCK + 400
1/fMCK + 400
ns
DAPmn = 1 2.7 V
≤ EVDD0 ≤ 5.5 V
120
120
120
ns
1.8 V
≤ EVDD0 ≤ 5.5 V
200
200
200
ns
1.7 V
≤ EVDD0 ≤ 5.5 V
400
400
400
ns
1.6 V
≤ EVDD0 ≤ 5.5 V
—
400
400
ns
SCKp
SOp
User's device
SCK
SI
SIp
SO
RL78 microcontroller
SCK00
SO00
User's device
SCK
SI
SI00
SO
SSI00
SSO
RL78 microcontroller



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