HT45F5Q datasheet(46/114 Pages) HOLTEK

46 / 114 page

Rev. 1.10

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Rev. 1.10

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HT45F5Q

Charger Flash MCU

HT45F5Q

Charger Flash MCU

“

CLR WDT”Inst�u�tion

8-stage Divide�

WDT P�es�ale�

WE4~WE0 �its

WDTC

Registe�

Reset MCU

fLIRC

fLIRC/�8

8-to-1 MUX

CLR

WS�~WS0

WDT Ti�e-out

(�8/fLIRC ~ �15/fLIRC)

“

HALT”Inst�u�tion

LIRC

RES pin �eset

Watchdog Timer

Reset and Initialisation

Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbeset

tosomepredeterminedconditionirrespectiveofoutsideparameters.Themostimportantreset

conditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywill

ensurethatthemicrocontroller,afterashortdelay,willbeinawelldefinedstateandreadyto

executethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisters

willbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgram

Counter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthe

lowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereitisnecessarytoforcefullyapply

aresetconditionwhenthemicrocontrollerisrunning.Oneexampleofthisiswhereafterpower

hasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.

Insuchacase,knownasanormaloperationreset,someofthemicrocontrollerregistersremain

unchangedallowingthemicrocontrollertoproceedwithnormaloperationaftertheresetlineis

allowedtoreturnhigh.

AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.All

typesofresetoperationsresultindifferentregisterconditionsbeingsetup.Anotherresetexistsinthe

formofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepower

supplyvoltagefallsbelowacertainthreshold.

Reset Functions

Thereareseveralwaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringboth

internallyandexternally:

Power-on Reset

Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedto

themicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirst

memoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknown

conditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthat

allpinswillbefirstsettoinputs.

RE S

VD D

In te r nal R es et

0. 9 V DD

t RS TD + t SST

Note:tRSTDispower-ondelay,typicaltime=50ms

Power-On Reset Timing Chart

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