GL813 - USB2.0 CompactFlash Card Reader Controller

©2001-2002 Genesys Logic Inc.—All rights reserved.

Page 17 of 24

5.2 Receive Operation

5.2.1 Receive State Diagram

RXACTV and RXVLD are sampled on the rising edge of CLKOUT.

In the RX Wait state the receiver is always looking for SYNC.

The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state).

The Macrocell negates RXACTV when an EOP is detected (Strip EOP state).

When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is

full.

RXVLD will be negated if the RX Holding Register was not loaded during the

previous byte time. This will occur if 8 stuffed bits have been accumulated.

The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted

(RX Data state).

In FS mode, if a bit stuff error is detected then the Receive State Machine will negate

RXACTV and RXVLD, and return to the RXWait state.

Reset

!RXACTV

!RXVLD

RX Wait

Trip SYNC

RXACTV

Rx Data

RXVLD

RX Data Wait

!RXVLD

Strip EOP

!RXACTV

!RXVLD

HRST#

!HRST#

SYNC Detected

Data

!Data

!SYNC

SYNC

Data

Data

Abort 1

!RXACTV

!RXVLD

!RXERR

Terminate

!RXACTV

Abort 2

!RXVLD

!RXERR

Error

RXERR

EOP

Detected

!Data

Receive

Error

!Idle

state

Idle

state