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NAND01GR3A bảng dữ liệu(PDF) 19 Page - STMicroelectronics |
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NAND01GR3A bảng dữ liệu(HTML) 19 Page - STMicroelectronics |
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19 / 57 page ![]() 19/57 NAND128-A, NAND256-A, NAND512-A, NAND01G-A COMMAND SET All bus write operations to the device are interpret- ed by the Command Interface. The Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are se- lected by writing specific commands to the Com- mand Register. The two-step command sequences for program and erase operations are imposed to maximize data security. The Commands are summarized in Table 9., Commands. Table 9. Commands Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown. 2. Any undefined command sequence will be ignored by the device. Command Bus Write Operations(1) Command accepted during busy 1st CYCLE 2nd CYCLE 3rd CYCLE Read A 00h - - Read B 01h(2) - - Read C 50h - - Read Electronic Signature 90h - - Read Status Register 70h - - Yes Page Program 80h 10h - Copy Back Program 00h 8Ah 10h Block Erase 60h D0h - Reset FFh - - Yes |
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