SC16C750B datasheet(21/44 Pages) PHILIPS

21 / 44 page

Philips Semiconductors

SC16C750B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Product data

Rev. 03 — 13 December 2004

21 of 44

9397 750 14453

7.4 Interrupt Status Register (ISR)

The SC16C750B provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values

(bits 0-4) for the four prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 12:

Interrupt source

Priority

level

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

0110

LSR (Receiver Line Status Register)

0100

RXRDY (Received Data Ready)

1100

RXRDY (Receive Data time-out)

0010

TXRDY (Transmitter Holding Register

Empty)

0000

MSR (Modem Status Register)

Table 13:

Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is

not being used. They are set to a logic 1 when the FIFOs are

enabled.

Logic 0 or cleared = default condition.

ISR[5]

64-byte FIFO enable.

Logic 0 = 16-byte operation.

Logic 1 = 64-byte operation.

ISR[4]

Not used.

3:1

ISR[3:1]

INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).

Logic 0 or cleared = default condition.

ISR[0]

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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