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STA339BWS bảng dữ liệu(PDF) 74 Page - STMicroelectronics

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Applications
STA339BWS
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DocID015276 Rev 8
8.2
PLL filter circuit
It is recommended to use the applications circuit and values for the PLL loop filter to achieve
the best performance from the device in general applications. Note that the ground of this
filter circuit has to be connected to the ground of the PLL without any resistive path.
Concerning the component values, it must be taken into account that the greater the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
8.3
Typical output configuration
Figure 24 shows the typical output configuration used for BTL stereo mode. Please contact
STMicroelectronics for other recommended output configurations.
Figure 24. Output configuration for stereo BTL mode (RL = 8 
OUT1A
100 nF
100 nF
100 nF
100 nF
6R2
6R2
330 pF
22R
OUT1B
22 μH
22 μH
Left
470 nF
OUT2A
100 nF
100 nF
100 nF
100 nF
6R2
6R2
330 pF
22R
OUT2B
22 μH
22 μH
Right
470 nF



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