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Revision 1.01

11 - 14

AS1372

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Improved dropout

Dropout mainly refers to the resistivity of the output transistor when its gate is driven to ground and the feedback

regulation loop is open. Moreover when the output transistor is in dropout input and output voltages are nearly

coincident. In this way, in a traditional approach, the gate to source voltage that determines the resistivity of the output

PMOS in dropout is nearly equal to the output voltage. This means that a smaller output voltage brings worse dropout

performances. In the dual supply approach, on the contrary, in dropout conditions the gate of the output transistor is

pushed to Vbias voltage and only Vin drops nearly coincident to Vout. As Vbias can be chosen independently from Vin,

even at small output voltages a large overdrive at the output transistor can be ensured and an extremely reduced

dropout value comes out.

Faster response

In a traditional approach, the output of the LDO is coincident with the drain of the output PMOS transistor. In this way,

if the load current suddenly changes, any variation at the output voltage is not able to vary the output current of the

LDO until it is amplified to the gate of the output PMOS by the error amplifier. A delay comes, unavoidably. On the

contrary, in the dual supply approach it is the source of the output transistor to be coincident with the output voltage. In

this way a change in the output voltage immediately modulates the current from the LDO and a better regulation in fast

load transient is achieved.