AS8C403625 datasheet(9/19 Pages) ALSC

9 / 19 page

AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

Linear Burst Sequence Table ( LBO=VSS)

Synchronous Write Function Truth Table (1, 2)

Asynchronous Truth Table (1)

Interleaved Burst Sequence Table ( LBO=VDD)

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

BW3 and BW4 are not applicable for the

AS8C401825.

3. Multiple bytes may be selected during the same cycle.

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

Operation

BWE

BW1

BW2

BW3

BW4

Read

XXXX

Read

HHHH

Write all Bytes

XXXXX

Write all Bytes

LLLLL

Write Byte 1(3)

HHH

Write Byte 2(3)

Write Byte 3(3)

Write Byte 4(3)

HHH

5280 tbl 12

Operation(2)

I/O Status

Power

Read

Data Out

Active

Read

High-Z

Active

Write

High-Z – Data In

Active

Deselected

High-Z

Standby

Sleep Mode

High-Z

Sleep

5280 tbl 13

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

000

Second Address

Third Address

Fourth Address(1)

111

5280 tbl 14

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

000

Second Address

Third Address

Fourth Address(1)

000

5280 tbl 15

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