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AS6C8016 bảng dữ liệu(PDF) 4 Page - Alliance Semiconductor Corporation |
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AS6C8016 bảng dữ liệu(HTML) 4 Page - Alliance Semiconductor Corporation |
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4 / 12 page ![]() AC TEST CONDITIONS Input Pulse Levels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE AS6C8016 PARAMETER SYM. UNIT Read Cycle Time tRC Address Access Time tAA Chip Enable Access Time tACE Output Enable Access Time tOE Chip Enable to Output in Low-Z tCLZ Output Enable to Output in Low-Z tOLZ Chip Disable to Output in High-Z tCHZ Output Disable to Output in High-Z tOHZ Output Hold from Address Change tOH LB#, UB# Access Time tBA LB#, UB# to High-Z Output tBHZ LB#, UB# to Low-Z Output tBLZ (2) WRITE CYCLE AS6C8016 PARAMETER UNIT Write Cycle Time tWC Address Valid to End of Write tAW Chip Enable to End of Write tCW Address Set-up Time tAS Write Pulse Width tWP Write Recovery Time tWR Data to Write Time Overlap tDW Data Hold from End of Write Time tDH Output Active from End of Write tOW Write to Output in High-Z tWHZ LB#, UB# Valid to End of Write tBW *These parameters are guaranteed by device characterization, but not production tested. 512K X 8 BIT LOW POWER CMOS SRAM January 2007 NOVEMBER 2007 NOVEMBER/2007, V 1.0 Alliance Memory Inc. Page 4 of 12 AS6C8016 512K X 16 BIT SUPER LOW POWER CMOS SRAM SYM. |
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