DS9034PCX datasheet(3/22 Pages) DALLAS

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DS1251/DS1251P

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RAM READ MODE

The DS1251 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is

active (low). The unique address specified by the 19 address inputs (A0–A18) defines which of the 512k

bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC

(access time) after the last address input signal is stable, providing that CE and OE (output enable) access

times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be

measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or

tOE for OE , rather than address access.

RAM WRITE MODE

The DS1251 is in the write mode whenever the WE and CE signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must

be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time

(tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active)

then WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.

However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch

point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC

operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.

The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.

When VCC falls below the power-fail point, VPF , access to the device is inhibited. If VPF is less than VBAT,

the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below VPF . If VPF is

greater than VBAT, the device power is switched from VCC to the backup supply (VBAT ) when VCC drops

below VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to

nominal levels.

All control, data, and address signals must be powered down when VCC is powered down.

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of

64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on

DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the

phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the

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