DP8473 datasheet(5/28 Pages) NSC

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Typical Application

TLF9384 – 4

Recommended Plastic Chip Carrier Socket

AMP PN 821551-1 or equivalent

FIGURE 2 DP8473 Typical Application

Functional Description

This section describes the basic architectural features of

the DP8473 and many of the enhancements provided Re-

fer to

Figure 1

765A COMPATIBLE MICRO-ENGINE

The core of the DP8473 is a mPD765A compatible micro-

coded engine This engine consists of a sequencer pro-

gram ROM and diskmisc registers This core is clocked by

either a 4 MHz 48 MHz or 8 MHz clock selected in the Data

Rate Register Upon this core is added all the glue logic

used to implement a PC-XT or AT or PS2 floppy controller

as well as the data separator and write precompensation

logic

The controller consists of a microcoded engine that controls

the entire operation of the chip including coordination of

data transfer with the CPU controlling the drive controls

and actually performing the algorithms associated with

reading and writing data tofrom the disk This includes the

read algorithm for the data separator

Like the mPD765A this controller takes commands and re-

turns data and status through the Data Register in a byte

serial fashion Handshake for commandstatus IO is pro-

vided via the Main Status Register All of the mPD765A

commands are supported as are many other enhanced

commands

DATA SEPARATOR

The internal data separator consists of an analog PLL and

its associated circuitry The PLL synchronizes the raw data

signal read from the disk drive The synchronized signal is

used to separate the encoded clock and data pulses The

data pulses are de-serialized into bytes and then sent to the

P by the controller

The main PLL consists of four main components a phase

comparator a filter a voltage controlled oscillator (VCO)

and a programmable divider The phase comparator detects

the difference between the phase of the divider’s output and

the phase of the raw data being read from the disk This

phase difference is converted to a current which either

charges or discharges one of the three external filters The

resulting voltage on the filter changes the frequency of the

VCO and the divider output to reduce the phase difference

between the input data and the divider’s output The PLL is

‘‘locked’’ when the frequency of the divider is exactly the

same as the average frequency of the data read from the

disk A block diagram of the data separator is shown in

Fig-

ure 3

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