TP3410 datasheet(4/32 Pages) NSC

4 / 32 page

Pin Descriptions (Continued)

Symbol

Description

The digital input for multiplexed B D and

control data clocked by BCLK at the rate

of 1 data bit per 2 BCLK cycles and 32

data bits per 8 kHz frame defined by FSa

The open-drain n-channel output for multi-

plexed B D and control data clocked by

BCLK at the rate of 1 data bit per 2 BCLK

cycles and 32 data bits per 8 kHz frame

defined by FSa A pull-up resistor is re-

quired to define the logical 1 state

FSa

In GCI Slave mode (MO connected low)

this pin is the 8 kHz Frame Sync pulse in-

put requiring a positive edge to indicate

the start of the GCI slot time for both

transmit and receive data at Bx and Br In

GCI Master mode this pin is the 8 kHz

Frame Sync CMOS output pulse

Symbol

Description

17 S2CLS

In GCI Slave mode (MO e 0)

19 S1

input pins S2 S1 and S0 together pro-

SOFSb

(

vide a 3-bit binary-coded select port for

the GCI channel number S2 is the msb

These pins must be connected either to

VCCD or GND to select the 1-of-8 GCI

slots which are available if BCLK t 4096

MHz is used

In GCI Master mode (MO e 1)

S2CLS is the GCI Clock Select input

Connect this pin high to select BCLK e

1536 MHz connect CLS low to select

BCLK e 512 kHz SOFSb is a Frame

Sync CMOS output pulse which identifies

the B2 channel

18 ES1

While in GCI mode the ES1 ES2 pins are

16 ES2

(

local input pins The status of the pins can

be accessed via the RXM56 register bits

56 corresponding to ES1 ES2

15 LEC

Latched External Control output which is

the output of a latched bit in the TXM56

TP3410 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

TP3410 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

bảng dữ liệu tải về

Link URL