ZLP32300P2016G datasheet(49/99 Pages) ZILOG

49 / 99 page

Crimzon® ZLP32300

Product Specification

PS020823-0208

Functional Description

When more than one interrupt is pending, priorities are resolved by a programmable

priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle

activates when an interrupt request is granted. As a result, all subsequent interrupts are

disabled, and the Program Counter and Status Flags are saved. The cycle then branches to

the program memory vector location reserved for that interrupt. All Crimzon ZLP32300

interrupts are vectored through locations in the program memory. This memory location

and the next byte contain the 16-bit address of the interrupt service routine for that

particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are

masked, and the Interrupt Request register is polled to determine which of the interrupt

requests require service.

An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is

mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge

triggered. These interrupts are programmable. The software can poll to identify the state of

the pin.

Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250),

bits D7 and D6. The configuration is indicated in Table 12.

Table 11. Interrupt Types, Sources, and Vectors

Name

Source

Vector Location

Comments

IRQ0

P32

0,1

External (P32), Rising, Falling Edge Triggered

IRQ1

P33

2,3

External (P33), Falling Edge Triggered

IRQ2

P31, TIN 4,5

External (P31), Rising, Falling Edge Triggered

IRQ3

T16

6,7

Internal

IRQ4

8,9

Internal

IRQ5

LVD

10,11

Internal

Table 12. IRQ Register

IRQ

Interrupt Edge

IRQ2 (P31)

IRQ0 (P32)

R/F

Note: F = Falling Edge; R = Rising Edge

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