STM32L471VG datasheet(159/218 Pages) STMICROELECTRONICS

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STM32L471xx

Electrical characteristics

199

tSAMP

Sampling time in sample

and hold mode (code

transition between the

lowest input code and the

highest input code when

DACOUT reaches final

value ±1LSB)

DAC_OUT

pin connected

DAC output buffer

ON, CSH = 100 nF

-0.7

3.5

DAC output buffer

OFF, CSH = 100 nF

-10.5

DAC_OUT

pin not

connected

(internal

connection

only)

DAC output buffer

OFF

-2

3.5

µs

Ileak

Output leakage current

Sample and hold mode,

DAC_OUT pin connected

-(3)

CIint

Internal sample and hold

capacitor

5.2

8.8

tTRIM

Middle code offset trim

time

DAC output buffer ON

µs

Voffset

Middle code offset for 1

trim code step

VREF+ = 3.6 V

1500

µV

VREF+ = 1.8 V

750

IDDA(DAC)

DAC consumption from

VDDA

DAC output

buffer ON

No load, middle

code (0x800)

315

500

µA

No load, worst code

(0xF1C)

450

670

DAC output

buffer OFF

No load, middle

code (0x800)

0.2

Sample and hold mode, CSH =

100 nF

315 ₓ

Ton/(Ton

+Toff)

(4)

670 ₓ

Ton/(Ton

+Toff)

(4)

IDDV(DAC)

DAC consumption from

VREF+

DAC output

buffer ON

No load, middle

code (0x800)

185

240

µA

No load, worst code

(0xF1C)

340

400

DAC output

buffer OFF

No load, middle

code (0x800)

155

205

Sample and hold mode, buffer ON,

CSH = 100 nF, worst case

185 ₓ

Ton/(Ton

+Toff)

(4)

400 ₓ

Ton/(Ton

+Toff)

(4)

Sample and hold mode, buffer OFF,

CSH = 100 nF, worst case

155 ₓ

Ton/(Ton

+Toff)

(4)

205 ₓ

Ton/(Ton

+Toff)

(4)

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Table 69. DAC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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