STM32F767II datasheet(47/255 Pages) STMICROELECTRONICS

47 / 255 page

DocID029041 Rev 4

47/255

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Functional overview

•

Software configurable to OTG1.3 and OTG2.0 modes of operation

•

USB 2.0 LPM (Link Power Management) support

•

Battery Charging Specification Revision 1.2 support

•

Internal FS OTG PHY support

•

External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

•

HNP/SNP/IP inside (no need for any external resistor)

•

for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

2.36

High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)

The devices embed a HDMI-CEC controller that provides hardware support for the

Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an

environment. It is specified to operate at low speeds with minimum processing and memory

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC

controller to wakeup the MCU from Stop mode on data reception.

2.37

Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS

sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera

interface can sustain a data transfer rate up to 54 Mbytes/s in 8-bit mode at 54 MHz. It

features:

•

Programmable polarity for the input pixel clock and synchronization signals

•

Parallel data communication can be 8-, 10-, 12- or 14-bit

•

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

•

Capability to automatically crop the image

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